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| 50 Hz to 6 GHz, 50 dB TruPwrTM Detector AD8363 FEATURES Accurate rms-to-dc conversion from 50 Hz to 6 GHz Single-ended input dynamic range of >50 dB No balun or external input tuning required Waveform and modulation independent, such as GSM/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE Linear-in-decibels output, scaled: 52 mV/dB Log conformance error: <0.15 dB Temperature stability: <0.5 dB Voltage supply range: 4.5 V to 5.5 V Operating temperature range: -40C to +125C Power-down capability to 1.5 mW Small footprint, 4 mm x 4 mm, LFCSP FUNCTIONAL BLOCK DIAGRAM VTGT 12 VREF 11 VPOS 10 COMM 9 NC 13 AD8363 8 TEMP X2 INHI 14 X2 INLO 15 6 7 VSET VOUT TCM1 16 5 CLPF 07368-001 APPLICATIONS Power amplifier linearization/control loops Transmitter power controls Transmitter signal strength indication (TSSI) RF instrumentation 1 2 3 4 TCM2/PWDN CHPF VPOS COMM Figure 1. GENERAL DESCRIPTION The AD8363 is a true rms responding power detector that can be directly driven with a single-ended 50 source. This feature makes the AD8363 frequency versatile by eliminating the need for a balun or any other form of external input tuning for operation up to 6 GHz. The AD8363 provides an accurate power measurement, independent of waveform, for a variety of high frequency communication and instrumentation systems. Requiring only a single supply of 5 V and a few capacitors, it is easy to use and provides high measurement accuracy. The AD8363 can operate from arbitrarily low frequencies to 6 GHz and can accept inputs that have rms values from less than -50 dBm to at least 0 dBm, with large crest factors exceeding the requirements for accurate measurement of WiMAX, CDMA, W-CDMA, TD-SCDMA, multicarrier GSM, and LTE signals. The AD8363 can determine the true power of a high frequency signal having a complex low frequency modulation envelope, or it can be used as a simple low frequency rms voltmeter. The highpass corner generated by its internal offset-nulling loop can be lowered by a capacitor added on the CHPF pin. Used as a power measurement device, VOUT is connected to VSET. The output is then proportional to the logarithm of the rms value of the input. The reading is presented directly in decibels and is conveniently scaled to 52 mV/dB, or approximately 1 V per decade; however, other slopes are easily arranged. In controller mode, the voltage applied to VSET determines the power level required at the input to null the deviation from the setpoint. The output buffer can provide high load currents. The AD8363 has 1.5 mW power consumption when powered down by a logic high applied to the TCM2/PWDN pin. It powers up within about 30 s to its nominal operating current of 60 mA at 25C. The AD8363 is available in a 4 mm x 4 mm 16-lead LFCSP for operation over the -40C to +125C temperature range. A fully populated RoHS-compliant evaluation board is also available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. AD8363 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 16 Square Law Detector and Amplitude Target .............................. 16 RF Input Interface ...................................................................... 17 Choice of RF Input Pin .............................................................. 17 Small Signal Loop Response ..................................................... 17 Temperature Sensor Interface ................................................... 18 VREF Interface ........................................................................... 18 Temperature Compensation Interface ..................................... 18 Power-Down Interface ............................................................... 19 VSET Interface ............................................................................ 19 Output Interface ......................................................................... 19 VTGT Interface .......................................................................... 20 Operation to 125C .................................................................... 20 Basis for Error Calculations ...................................................... 20 Measurement Mode Basic Connections.................................. 21 Device Calibration and Error Calculation .............................. 22 Selecting and Increasing Calibration Points to Improve Accuracy over a Reduced Range .............................................. 22 Altering the Slope ....................................................................... 23 Offset Compensation/Minimum CLPF and Maximum CHPF Capacitance Values..................................................................... 24 Choosing a Value for CLPF.......................................................... 25 RF Pulse Response ..................................................................... 27 Controller Mode Basic Connections ....................................... 27 Constant Output Power Operation.......................................... 28 Description of RF Characterization ......................................... 29 Evaluation and Characterization Circuit Board Layouts ...... 30 Assembly Drawings .................................................................... 32 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33 REVISION HISTORY 5/09--Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD8363 SPECIFICATIONS VPOS = 5 V, TA = 25C, ZO = 50 , single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, error referred to best-fit line (linear regression) from -20 dBm to -40 dBm, unless otherwise noted. Negative current values imply that the AD8363 is sourcing current out of the indicated pin. Table 1. Parameter OVERALL FUNCTION Maximum Input Frequency RF INPUT INTERFACE Input Resistance Common-Mode DC Voltage 100 MHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Conditions Min Typ Max 6 INHI (Pin 14), INLO (Pin 15), ac-coupled Single-ended drive TCM1 (Pin 16) = 0.47 V, TCM2 (Pin 1) = 1.0 V, INHI input PIN = -10 dBm PIN = -40 dBm CW input, TA = 25C 50 2.6 2.47 0.92 65 9 -56 -0.2/+0.3 -0.5/+0.6 51.7 -58 <0.1 <0.1 <0.1 <0.1 49 - j0.09 2.2 0.91 54 -2 -56 +0.6/-0.4 +0.8/-0.6 51.8 -58 <0.1 <0.1 <0.1 <0.1 60 - j3.3 Unit GHz V V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 900 MHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature 13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic range 256 QAM, CF = 8 dB, over 40 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.5 V, TCM2 (Pin 1) = 1.2 V, INHI input PIN = -15 dBm PIN = -40 dBm CW input, TA = 25C Deviation from output at 25C -40C < TA < +85C; PIN = -15 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 13 dB peak-to-rms ratio (W-CDMA), over 40 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 40 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 40 dB dynamic range 256 QAM, CF = 8 dB, over 40 dB dynamic range Single-ended drive Rev. 0 | Page 3 of 36 AD8363 Parameter 1.9 GHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Conditions TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.51 V, INHI input PIN = -15 dBm PIN = -40 dBm CW input, TA = 25C Min Typ 2.10 0.8 48 -6 -54 +0.3/-0.5 +0.4/-0.4 52 -55 0.1 0.1 0.1 0.1 118 - j26 2.0 0.71 44 -8 -52 +0.1/-0.2 +0.3/-0.5 52.2 -54 0.1 0.1 0.1 0.1 3 15 130 - j49 1.84 0.50 41 -7 -48 +0.5/-0.2 +0.6/-0.2 52.9 -49 Max Unit V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB s s V V dB dBm dBm dB dB mV/dB dBm Deviation from output at 25C -40C < TA < +85C; PIN = -15 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 2.14 GHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature 13 dB peak-to-rms ratio (W-CDMA), over 37 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 37 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 37 dB dynamic range 256 QAM, CF = 8 dB, over 37 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.52 V, TCM2 (Pin 1) = 0.6 V, INHI input PIN = -15 dBm PIN = -40 dBm CW input, TA = 25C Deviation from output at 25C -40C < TA < +85C; PIN = -15 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Rise Time Fall Time Input Impedance 2.6 GHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature 13 dB peak-to-rms ratio (W-CDMA), over 35 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 35 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 35 dB dynamic range 256 QAM, CF = 8 dB, over 35 dB dynamic range Transition from no input to 1 dB settling at RFIN = -10 dBm, CLPF = 390 pF, CHPF = open Transition from -10 dBm to within 1 dB of final value (that is, no input level), CLPF = 390 pF, CHPF = open Single-ended drive TCM1 (Pin 16) = 0.54 V, TCM2 (Pin 1) = 1.1 V, INHI input PIN = -15 dBm PIN = -40 dBm CW input, TA = 25C Deviation from output at 25C -40C < TA < +85C; PIN = -15 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Rev. 0 | Page 4 of 36 AD8363 Parameter Deviation from CW Response Conditions 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.56 V, TCM2 (Pin 1) = 1.0 V, INLO input PIN = -20 dBm PIN = -40 dBm CW input, TA = 25C Min Typ 0.1 0.1 0.1 0.1 95 - j65 1.54 0.54 43 -5 -48 +0.1/-0.7 +0.4/-0.5 50.0 -51 0.1 0.1 0.1 0.1 42 - j4.5 1.38 0.36 45 -3 -48 +0.1/-0.6 +0.3/-0.8 51.1 -47 0.1 0.1 0.1 0.1 28 + j1.6 0.03 4.8 10/10 -0.2/+0.1 3 15 45 Max Unit dB dB dB dB V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB V V dB dBm dBm dB dB mV/dB dBm dB dB dB dB V V mA % s s nV/Hz Input Impedance 3.8 GHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Deviation from output at 25C -40C < TA < +85C; PIN = -20 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance 5.8 GHz Output Voltage: High Power In Output Voltage: Low Power In 1.0 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive TCM1 (Pin 16) = 0.88 V, TCM2 (Pin 1) = 1.0 V, INLO input PIN = -20 dBm PIN = -40 dBm CW input, TA = 25C Deviation from output at 25C -40C < TA < +85C; PIN = -20 dBm -40C < TA < +85C; PIN = -40 dBm Logarithmic Slope Logarithmic Intercept Deviation from CW Response Input Impedance OUTPUT INTERFACE Output Swing, Controller Mode Current Source/Sink Capability Voltage Regulation Rise Time Fall Time Noise Spectral Density 13 dB peak-to-rms ratio (W-CDMA), over 32 dB dynamic range 12 dB peak-to-rms ratio (WiMAX), over 32 dB dynamic range 14.0 dB peak-to-rms ratio (16C CDMA2K), over 32 dB dynamic range 256 QAM, CF = 8 dB, over 32 dB dynamic range Single-ended drive VOUT (Pin 6) Swing range minimum, RL 500 to ground Swing range maximum, RL 500 to ground Output held at VPOS/2 ILOAD = 8 mA, source/sink Transition from no input to 1 dB settling at RFIN = -10 dBm, CLPF = 390 pF, CHPF = open Transition from -10 dBm to within 1 dB of final value (that is, no input level), CLPF = 390 pF, CHPF = open Measured at 100 kHz Rev. 0 | Page 5 of 36 AD8363 Parameter SETPOINT INPUT Voltage Range Input Resistance Logarithmic Scale Factor Logarithmic Intercept TEMPERATURE COMPENSATION Input Voltage Range Input Bias Current, TCM1 Input Resistance, TCM1 Input Current, TCM2 Conditions VSET (Pin 7) Log conformance error 1 dB, minimum 2.14 GHz Log conformance error 1 dB, maximum 2.14 GHz f = 2.14 GHz, -40C TA +85C f = 2.14 GHz, -40C TA +85C, referred to 50 TCM1 (Pin 16), TCM2 (Pin 1) 0 VTCM1 = 0 V VTCM1 = 0.5 V VTCM1 > 0.7 V VTCM2 = 5 V VTCM2 = 4.5 V VTCM2 = 1 V VTCM2 = 0 V 0.7 V VTCM2 4.0 V VREF (Pin 11) RFIN = -55 dBm 25C TA 70C 70C TA 125C -40C TA +25C 25C TA 125C -40C TA < +25C TA = 25C, ILOAD = 3 mA TEMP (Pin 8) TA = 25C, RL 10 k -40C TA +125C, RL 10 k 25C TA 125C -40C TA < +25C TA = 25C, ILOAD = 3 mA VTGT (Pin 12) 1.4 VTGT = 1.4 V TCM2 (Pin1) VPWDN decreasing VPWDN increasing VTCM2 = 5 V VTCM2 = 4.5 V VTCM2 = 1 V VTCM2 = 0 V TCM2 low to VOUT at 1 dB of final value, CLPF = 470 pF, CHPF = 220 pF, RFIN = 0 dBm TCM2 high to VOUT at 1 dB of final value, CLPF = 470 pF, CHPF = 220 pF, RFIN = 0 dBm VPOS (Pin 3, Pin 10) 4.5 TA = 25C, RFIN = -55 dBm TA = 85C VTCM2 > VPOS - 0.3 V 14 100 4.2 4.7 2 750 -2 -3 35 25 -140 80 5 2 750 -2 -3 500 2.3 0.04 -0.06 -0.18 4/0.05 3/0.05 -0.6 1.4 5 4/0.05 3/0.05 -0.1 2.5 Min Typ 2.0 0.7 72 19.2 -54 2.5 Max Unit V V k dB/V dBm V A A k A A A A k V mV/C mV/C mV/C mA mA % V mV/C mA mA % V A k V V A A A A s s Input Resistance, TCM2 VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Current Source/Sink Capability Voltage Regulation TEMPERATURE REFERENCE Output Voltage Temperature Coefficient Current Source/Sink Capability Voltage Regulation RMS TARGET INTERFACE Input Voltage Range Input Bias Current Input Resistance POWER-DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current Enable Time Disable Time POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Power-Down Current 5 60 72 300 5.5 V mA mA A Rev. 0 | Page 6 of 36 AD8363 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS Input Average RF Power 1 Equivalent Voltage, Sine Wave Input Internal Power Dissipation JC 2 JB2 JA2 JT2 JB2 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) 1 Rating 5.5 V 21 dBm 2.51 V rms 450 mW 10.6C/W 35.3C/W 57.2C/W 1.0C/W 34C/W 150C -40C to +125C -65C to +150C 300C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This is for long durations. Excursions above this level, with durations much less than 1 second, are possible without damage. 2 No airflow with the exposed pad soldered to a 4-layer JEDEC board. Rev. 0 | Page 7 of 36 AD8363 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 TCM1 15 INLO 14 INHI 13 NC TCM2/PWDN 1 CHPF 2 VPOS 3 COMM 4 PIN 1 INDICATOR 12 VTGT 11 VREF 10 VPOS 9 COMM AD8363 TOP VIEW (Not to Scale) VOUT 6 TEMP 8 VSET 7 CLPF 5 NOTES 1. NC = NO CONNECT Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic TCM2/PWDN Description This is a dual function pin used for controlling the amount of nonlinear intercept temperature compensation at voltages <2.5 V and/or for shutting down the device at voltages >4 V. If the shutdown function is not used, this pin can be connected to the VREF pin through a voltage divider. Connect this pin to VPOS via a capacitor to determine the -3 dB point of the input signal high-pass filter. Only add a capacitor when operating at frequencies below 10 MHz. Supply for the Device. Connect these pins to a 5 V power supply. Pin 3 and Pin 10 are not internally connected; therefore, both must connect to the source. System Common Connection. Connect these pins via low impedance to system common. The exposed paddle is also COMM and should have both a good thermal and good electrical connection to ground. Connection for Loop Filter Integration (Averaging) Capacitor. Connect a ground-referenced capacitor to this pin. A resistor can be connected in series with this capacitor to improve loop stability and response time. Minimum CLPF value is 390 pF. Output Pin in Measurement Mode (Error Amplifier Output). In measurement mode, this pin is connected to VSET. This pin can be used to drive a gain control when the device is used in controller mode. The voltage applied to this pin sets the decibel value of the required RF input voltage that results in zero current flow in the loop integrating capacitor pin, CLPF. This pin controls the variable gain amplifier (VGA) gain such that a 50 mV change in VSET reduces the gain by approximately 1 dB. Temperature Sensor Output. General-Purpose Reference Voltage Output of 2.3 V. The voltage applied to this pin determines the target power at the input of the RF squaring circuit. The intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity; however, this may affect the system loop response. No Connect. This is the RF input pin for frequencies up to and including 2.6 GHz. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. This is the RF input pin for frequencies above 2.6 GHz. The RF input signal is normally ac-coupled to this pin through a coupling capacitor. This pin is used to adjust the intercept temperature compensation. Connect this pin to VREF through a voltage divider or to an external dc source. Equivalent Circuit See Figure 49 2 3, 10 4, 9, EPAD 5 CHPF VPOS COMM 07368-002 See Figure 60 N/A N/A CLPF See Figure 51 6 VOUT See Figure 51 7 VSET See Figure 50 8 11 12 TEMP VREF VTGT See Figure 45 See Figure 46 See Figure 52 13 14 15 16 NC INHI INLO TCM1 N/A See Figure 44 See Figure 44 See Figure 48 Rev. 0 | Page 8 of 36 AD8363 TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 5 V, ZO = 50 , single-ended input drive, VOUT connected to VSET, VTGT = 1.4 V, CLPF = 3.9 nF, CHPF = 2.7 nF, TA = +25C (black), -40C (blue), +85C (red), where appropriate. Error referred to best-fit line (linear regression) from -20 dBm to -40 dBm, unless otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated. 4 INHI INPUT VTCM1 = 0.47V, VTCM2 = 1V 5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3 1 4 ERROR (dB) 07368-008 2 6 INHI INPUT VTCM1 = 0.5V, VTCM2 = 1.2V 2 1 2 ERROR (dB) 0 3 0 2 -1 1 1 -1 07368-003 -50 -40 -30 -20 PIN (dBm) -10 0 -50 -40 -30 -20 PIN (dBm) -10 0 Figure 3. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 100 MHz, CW, Typical Device 4 INHI INPUT VTCM1 = 0.47V, VTCM2 = 1V REPRESENTS 35 DEVICES FROM 3 LOTS OUTPUT VOLTAGE (V) 2 Figure 6. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 900 MHz, CW, Typical Device 6 INHI INPUT VTCM1 = 0.5V, VTCM2 = 1.2V REPRESENTS 35 DEVICES FROM 3 LOTS 1 OUTPUT VOLTAGE (V) 4 ERROR (dB) 07368-007 2 5 1 3 2 ERROR (dB) 0 3 0 2 -1 1 1 -1 -50 -40 -30 -20 PIN (dBm) -10 0 07368-004 0 -60 -2 10 0 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -2 10 Figure 4. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 100 MHz, CW 2 INHI INPUT VTCM1 = 0.47V, VTCM2 = 1V REPRESENTS 35 DEVICES FROM 3 LOTS 1 Figure 7. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 900 MHz, CW 2 INHI INPUT VTCM1 = 0.5V, VTCM2 = 1.2V REPRESENTS 35 DEVICES FROM 3 LOTS 1 ERROR (dB) 0 ERROR (dB) 0 -1 -1 -50 -40 -30 -20 PIN (dBm) -10 0 10 07368-005 -2 -60 -2 -60 -50 -40 -30 -20 PIN (dBm) -10 0 10 Figure 5. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 100 MHz, CW Figure 8. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 900 MHz, CW Rev. 0 | Page 9 of 36 07368-006 0 -60 -2 10 0 -60 -2 10 AD8363 6 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.51V 5 OUTPUT VOLTAGE (V) 2 OUTPUT VOLTAGE (V) 5 3 6 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.6V 2 3 4 1 ERROR (dB) 4 1 ERROR (dB) 07368-014 3 0 3 0 2 -1 2 -1 1 -2 1 -2 07368-009 -50 -40 -30 -20 PIN (dBm) -10 0 -50 -40 -30 -20 PIN (dBm) -10 0 Figure 9. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 1.90 GHz, CW, Typical Device 6 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.51V REPRESENTS 35 DEVICES FROM 3 LOTS 3 Figure 12. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 2.14 GHz, CW, Typical Device 6 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.6V REPRESENTS 35 DEVICES FROM 3 LOTS 3 5 OUTPUT VOLTAGE (V) 2 OUTPUT VOLTAGE (V) 5 2 4 1 ERROR (dB) 4 1 ERROR (dB) 07368-013 3 0 3 0 2 -1 2 -1 1 -2 1 -2 -50 -40 -30 -20 PIN (dBm) -10 0 07368-010 0 -60 -3 10 0 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -3 10 Figure 10. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 1.90 GHz, CW 3 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.51V REPRESENTS 35 DEVICES FROM 3 LOTS Figure 13. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 2.14 GHz, CW 3 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.6V REPRESENTS 35 DEVICES FROM 3 LOTS 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 -50 -40 -30 -20 PIN (dBm) -10 0 10 07368-011 -3 -60 -3 -60 -50 -40 -30 -20 PIN (dBm) -10 0 10 Figure 11. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 1.90 GHz, CW Figure 14. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 2.14 GHz, CW Rev. 0 | Page 10 of 36 07368-012 0 -60 -3 10 0 -60 -3 10 AD8363 6 INHI INPUT VTCM1 = 0.54V, VTCM2 = 1.1V 5 OUTPUT VOLTAGE (V) 2 2.5 3 3.0 INLO INPUT VTCM1 = 0.56V, VTCM2 = 1.0V 2 3 4 1 ERROR (dB) OUTPUT VOLTAGE (V) 2.0 1 3 0 1.5 0 2 -1 1.0 -1 1 -2 0.5 -2 07368-015 -50 -40 -30 -20 PIN (dBm) -10 0 -50 -40 -30 -20 PIN (dBm) -10 0 Figure 15. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 2.6 GHz, CW, Typical Device 6 INHI INPUT VTCM1 = 0.54V, VTCM2 = 1.1V REPRESENTS 35 DEVICES FROM 3 LOTS 3 Figure 18. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 3.8 GHz, CW, Typical Device 3.0 INLO INPUT VTCM1 = 0.56V, VTCM2 = 1.0V REPRESENTS 35 DEVICES FROM 3 LOTS 3 5 OUTPUT VOLTAGE (V) 2 2.5 2 4 1 ERROR (dB) OUTPUT VOLTAGE (V) 2.0 1 3 0 1.5 0 2 -1 1.0 -1 1 -2 0.5 -2 07368-016 -50 -40 -30 -20 PIN (dBm) -10 0 -50 -40 -30 -20 PIN (dBm) -10 0 Figure 16. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 2.6 GHz, CW 3 INHI INPUT VTCM1 = 0.54V, VTCM2 = 1.1V REPRESENTS 35 DEVICES FROM 3 LOTS Figure 19. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 3.8 GHz, CW 3 INLO INPUT VTCM1 = 0.56V, VTCM2 = 1.0V REPRESENTS 35 DEVICES FROM 3 LOTS 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 -50 -40 -30 -20 PIN (dBm) -10 0 10 -50 -40 -30 -20 PIN (dBm) -10 0 10 Figure 17. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 2.6 GHz, CW Figure 20. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 3.8 GHz, CW Rev. 0 | Page 11 of 36 07368-020 07368-017 -3 -60 -3 -60 07368-019 0 -60 -3 10 0 -60 -3 10 ERROR (dB) 07368-018 0 -60 -3 10 0 -60 -3 10 ERROR (dB) AD8363 3.0 INLO INPUT VTCM1 = 0.88V, VTCM2 = 1.0V 2.5 2 3 OUTPUT VOLTAGE (V) 2.0 1 ERROR (dB) 1.5 0 100MHz 900MHz 1.9GHz 2.14GHz 3.8GHz 1.0 -1 5.8GHz 0.5 -2 2.6GHz 07368-021 0 -60 -50 -40 Figure 21. VOUT and Log Conformance Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 5.8 GHz, Typical Device 3.0 INLO INPUT VTCM1 = 0.88V, VTCM2 = 1.0V REPRESENTS 35 DEVICES FROM 3 LOTS 3 Figure 24. Single-Ended Input Impedance (S11) vs. Frequency; ZO = 50 , INHI or INLO REPRESENTS APPROXIMATELY 3000 PARTS FROM SIX LOTS 2.5 2 800 OUTPUT VOLTAGE (V) 2.0 1 1.5 0 ERROR (dB) QUANTITY 600 400 1.0 -1 200 0.5 -2 07368-022 0 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -3 10 1.36 1.38 1.40 VTEMP (V) 1.42 1.44 1.46 Figure 22. Distribution of VOUT and Error with Respect to 25C Ideal Line over Temperature vs. Input Amplitude at 5.8 GHz, CW 3 INLO INPUT VTCM1 = 0.88V, VTCM2 = 1.0V REPRESENTS 35 DEVICES FROM 3 LOTS Figure 25. Distribution of VTEMP Voltage at 25oC, No RF Input 2.00 1.75 1.50 4 3 2 1 0 -1 -2 -3 07368-027 2 1 ERROR (dB) 0 1.00 0.75 -1 0.50 -2 0.25 07368-023 -3 -60 -50 -40 -30 -20 PIN (dBm) -10 0 10 -4 0 -50-40-30-20-10 0 10 20 30 40 50 60 70 80 90 100 110 120130 TEMPERATURE (C) Figure 23. Distribution of Error with Respect to 25C over Temperature vs. Input Amplitude at 5.8 GHz, CW Figure 26. VTEMP and Error with Respect to Straight Line vs. Temperature for Eleven Devices Rev. 0 | Page 12 of 36 ERROR (C) 1.25 VTEMP (V) 07368-077 0 1.34 07368-030 -30 -20 PIN (dBm) -10 0 -3 10 AD8363 3 ERROR CW ERROR CDMA2K PILOT CH SR1 ERROR CDMA2K 9CH SR1 ERROR CDMA2K 3 CAR 9CH SR1 ERROR CDMA2K 4 CAR 9CH SR1 3 ERROR CW ERROR W-CDMA 1 CAR TM1 64 DPCH ERROR W-CDMA 2 CAR TM1 64 DPCH ERROR W-CDMA 3 CAR TM1 64 DPCH ERROR W-CDMA 4 CAR TM1 64 DPCH 2 2 1 1 ERROR (dB) 07368-024 ERROR (dB) 0 0 -1 -1 -2 -2 -50 -40 -30 -20 PIN (dBm) -10 0 10 -50 -40 -30 -20 PIN (dBm) -10 0 10 Figure 27. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 900 MHz, CLPF = 0.1 F, INHI Input 3 ERROR CW ERROR CDMA2K 3 CAR 9CH SR1 ERROR CDMA2K 4 CAR 9CH SR1 Figure 30. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 2.14 GHz, CLPF = 0.1 F, INHI Input 3 2 2 1 1 ERROR (dB) 0 ERROR (dB) 0 -1 -1 -2 -2 CW W-CDMA 1 CAR TM1 32 DPCH QPSK 256QAM WIMAX 256 SUBCR, 64 QAM, 10MHz BW CDMA2K 9 CH SR1 4 CAR -50 -40 -30 -20 PIN (dBm) -10 0 10 07368-028 -50 -40 -30 -20 PIN (dBm) -10 0 10 07368-025 -3 -60 -3 -60 Figure 28. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 1.9 GHz, CLPF = 0.1 F, INHI Input 160 140 120 Figure 31. Error from CW Linear Reference vs. Input Amplitude with Modulation, Frequency at 2.6 GHz, CLPF = 0.1 F, INHI Input 1.0 INHI INPUT VTCM1 = 0.52V VTCM2 = 0.6V 0.5 NOISE SPECTRAL DENSITY (nV/ Hz) ERROR (dB) 100 80 60 40 20 07368-031 0 -0.5 4.50V 4.75V 5.00V 5.25V 5.50V 07368-032 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M -1.0 -60 -50 -40 -30 PIN (dBm) -20 -10 0 Figure 29. Typical Noise Spectral Density of VOUT; All CLPF Values Figure 32. Output Stability at 2.14 GHz with VPOS Variation, Error Normalized to Response at 5 V, VTGT = 1.4 V (Fixed) Rev. 0 | Page 13 of 36 07368-026 -3 -60 -3 -60 AD8363 5.0 0dBm 4.5 4.0 3.5 3.0 RF ENVELOPE -10dBm -20dBm -30dBm -40dBm 4.5 4.0 3.5 3.0 RF ENVELOPE 5.0 0dBm -10dBm -20dBm -30dBm -40dBm VOUT (V) 2.0 1.5 1.0 0.5 0 -0.5 07368-033 VOUT (V) 2.5 2.5 2.0 1.5 1.0 0.5 0 -0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TIME (s) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 TIME (s) Figure 33. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 390 pF, CHPF = Open, Rising Edge 5.0 4.5 4.0 3.5 3.0 RF ENVELOPE Figure 36. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 390 pF, CHPF = Open, Falling Edge 5.0 4.5 4.0 3.5 3.0 0dBm -10dBm -20dBm -30dBm -40dBm RF ENVELOPE VOUT (V) 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1 0 1 0dBm -10dBm -20dBm -30dBm -40dBm 07368-034 VOUT (V) 2.5 2.5 2.0 1.5 1.0 0.5 0 -0.5 2 TIME (ms) 3 4 5 0 1 TIME (ms) 2 3 4 Figure 34. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 0.1 F, CHPF = Open, Rising Edge 6 6 Figure 37. Output Response to RF Burst Input, Carrier Frequency at 2.14 GHz, CLPF = 0.1 F, CHPF = Open, Falling Edge 100 VTCM2 INCREASING 5 3 TCM2 LOW TCM2 HIGH 0 0dBm OUTPUT VOLTAGE, VOUT (V) VTCM2 (V) SUPPLY CURRENT (mA) 4 10 VTCM2 DECREASING 3 2 1 1 -50dBm 07368-037 4.1 4.2 4.3 4.4 TIME (s) 4.5 4.6 VTCM2 (V) 4.7 4.8 4.9 5.0 Figure 35. Output Response Using Power-Down Mode for Various RF Input Levels Carrier Frequency at 2.14 GHz, CLPF = 470 pF, CHPF = 220 pF Figure 38. Supply Current vs. VTCM2 Rev. 0 | Page 14 of 36 07368-051 0 -50 -25 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 0.1 4.0 07368-036 -1.0 -1 07368-035 -1.0 -2 -1 0 -1.0 -2 AD8363 2.325 600 REPRESENTS APPROXIMATELY 3000 PARTS FROM SIX LOTS 2.320 500 2.315 QUANTITY 400 300 VREF (V) 07368-029 2.310 2.305 2.300 200 100 2.295 2.290 -40 2.26 2.28 2.30 VREF (V) 2.32 2.34 2.36 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 Figure 39. Distribution of VREF, 25C, No RF Input 2.320 2.318 2.316 Figure 41. Change in VREF with Temperature for Eleven Devices 2.34 2.33 2.32 2.314 VREF (V) 2.310 2.308 2.306 VREF (V) 2.312 2.31 2.30 2.29 2.28 2.304 2.302 07368-038 2.27 07368-049 2.300 4.5 4.6 4.7 4.8 4.9 5.0 5.1 VPOS (V) 5.2 5.3 5.4 5.5 2.26 -30 -25 -20 -15 -10 -5 PIN (dBm) 0 5 10 Figure 40. Change in VREF with VPOS for Nine Devices Figure 42. Change in VREF with Input Amplitude for Eleven Devices Rev. 0 | Page 15 of 36 07368-048 0 2.24 AD8363 THEORY OF OPERATION The AD8363 is a 6 GHz, true rms responding detector with a 40 dB measurement range at 6 GHz and a greater than 50 dB measurement range at frequencies less than 1 GHz. It incorporates a modified AD8362 architecture that increases the frequency range and improves measurement accuracy at high frequencies. Log conformance peak-to-peak ripple has been reduced to <0.1 dB over the entire dynamic range. Temperature stability of the rms output measurements provides <0.5 dB error typically over the specified temperature range of -40C to 85C through proprietary techniques. The AD8363 is an rms-to-dc converter capable of operating on signals of approximately 50 Hz to 6 GHz or more. Unlike logarithmic amplifiers, the AD8363 response is waveform independent. The device accurately measures waveforms that have a high peak-to-rms ratio (crest factor). The AD8363 consists of a high performance AGC loop. As shown in Figure 43, the AGC loop comprises a wide bandwidth variable gain amplifier (VGA), square law detectors, an amplitude target circuit, and an output driver. For a more detailed description of the functional blocks, see the AD8362 data sheet. The nomenclature used in this data sheet to distinguish between a pin name and the signal on that pin is as follows: * * The pin name is all upper cased, for example, VPOS, COMM, and VOUT. The signal name or a value associated with that pin is the pin mnemonic with a partial subscript, for example, CLPF, CHPF, and VOUT. SQUARE LAW DETECTOR AND AMPLITUDE TARGET The VGA gain has the form GSET = GO exp(-VSET/VGNS) (1) where: GO is the basic fixed gain. VGNS is a scaling voltage that defines the gain slope (the decibel change per voltage). The gain decreases with increasing VSET. The VGA output is VSIG = GSET x RFIN = GO x RFIN exp(VSET/VGNS) (2) where RFIN is the ac voltage applied to the input terminals of the AD8363. The output of the VGA, VSIG, is applied to a wideband square law detector. The detector provides the true rms response of the RF input signal, independent of waveform. The detector output, ISQR, is a fluctuating current with positive mean value. The difference between ISQR and an internally generated current, ITGT, is integrated by CF and the external capacitor attached to the CLPF pin at the summing node. CF is an on-chip 25 pF filter capacitor, and CLPF, the external capacitance connected to the CLPF pin, can be used to arbitrarily increase the averaging time while trading off with the response time. When the AGC loop is at equilibrium Mean(ISQR) = ITGT This equilibrium occurs only when Mean(VSIG2) = VTGT2 (4) where VTGT is the voltage presented at the VTGT pin. This pin can conveniently be connected to the VREF pin through a voltage divider to establish a target rms voltage VATG of ~70 mV rms, when VTGT = 1.4 V. Because the square law detectors are electrically identical and well matched, process and temperature dependant variations are effectively cancelled. (3) INHI VGA INLO GSET VSET VSIG X2 SUMMING NODE ISQR ITGT VATG = X2 VTGT 20 VTGT CLPF CLPF (EXTERNAL) CF (INTERNAL) VOUT COMM VPOS CH (INTERNAL) CHPF CHPF (EXTERNAL) TEMPERATURE COMPENSATION AND BIAS TEMPERATURE SENSOR BAND GAP REFERENCE TCM1 TCM2/PWDN TEMP (1.4V) 07368-076 VREF (2.3V) Figure 43. Simplified Architecture Details Rev. 0 | Page 16 of 36 AD8363 By forcing the previous identity through varying the VGA setpoint, it is apparent that RMS(VSIG) = (Mean(VSIG2)) = (VATG2) = VATG Substituting the value of VSIG from Equation 2 results in ESD VPOS ESD INHI VBIAS ESD INLO 2.5k 50 ESD ESD ESD ESD ESD ESD ESD ESD ESD ESD ESD ESD ESD ESD 07368-039 (5) (6) 2.5k RMS(G0 x RFIN exp(-VSET/VGNS)) = VATG When connected as a measurement device, VSET = VOUT. Solving for VOUT as a function of RFIN VOUT = VSLOPE x log10(RMS(RFIN)/VZ) where: VSLOPE is 1 V/decade (or 50 mV/dB). VZ is the intercept voltage. When RMS(RFIN) = VZ, because log10(1) = 0, this implies that VOUT = 0 V, making the intercept the input that forces VOUT = 0 V. VZ has been fixed to approximately 280 V (approximately -58 dBm, referred to 50 ) with a CW signal at 100 MHz. In reality, the AD8363 does not respond to signals less than ~-56 dBm. This means that the intercept is an extrapolated value outside the operating range of the device. If desired, the effective value of VSLOPE can be altered by using a resistor divider between VOUT and VSET. (Refer to the Altering the Slope section for more information.) In most applications, the AGC loop is closed through the setpoint interface and the VSET pin. In measurement mode, VOUT is directly connected to VSET. (See the Measurement Mode Basic Connections section for more information.) In controller mode, a control voltage is applied to VSET and the VOUT pin typically drives the control input of an amplification or attenuation system. In this case, the voltage at the VSET pin forces a signal amplitude at the RF inputs of the AD8363 that balances the system through feedback. (See the Controller Mode Basic Connections section for more information.) (7) Figure 44. RF Inputs Simplified Schematic Extensive ESD protection is employed on the RF inputs, which limits the maximum possible input amplitude to the AD8363. CHOICE OF RF INPUT PIN The dynamic range of the AD8363 can be optimized by choosing the correct RF input pin for the intended frequency of operation. Using INHI (Pin 14), users can obtain the best dynamic range at frequencies up to 2.6 GHz. Above 2.6 GHz, it is recommended that INLO (Pin 15) be used. At 2.6 GHz, the performance obtained at the two inputs is approximately equal. The AD8363 was designed with a single-ended RF drive in mind. A balun can be used to drive INHI and INLO differentially, but it is not necessary, and it does not result in improved dynamic range. SMALL SIGNAL LOOP RESPONSE The AD8363 uses a VGA in a loop to force a squared RF signal to be equal to a squared dc voltage. This nonlinear loop can be simplified and solved for a small signal loop response. The lowpass corner pole is given by FreqLP 1.83 x ITGT/(CLPF) where: ITGT is in amperes. CLPF is in farads. FreqLP is in hertz. ITGT is derived from VTGT; however, ITGT is a squared value of VTGT multiplied by a transresistance, namely ITGT = gm x VTGT2 (10) gm is approximately 18.9 s, so with VTGT equal to the typically recommended 1.4 V, ITGT is approximately 37 A. The value of this current varies with temperature; therefore, the small signal pole varies with temperature. However, because the RF squaring circuit and dc squaring circuit track with temperature, there is no temperature variation contribution to the absolute value of VOUT. For CW signals, FreqLP 67.7 x 10-6/(CLPF) (11) However, signals with large crest factors include low pseudorandom frequency content that either needs to be filtered out or sampled and averaged out. See the Choosing a Value for CLPF section for more information. (9) RF INPUT INTERFACE Figure 44 shows the connections of the RF inputs within the AD8363. The input impedance is set primarily by an internal 50 resistor connected between INHI and INLO. A dc level of approximately half the supply voltage on each pin is established internally. Either the INHI pin or the INLO pin can be used as the single-ended RF input pin. (See the Choice of RF Input Pin section.) If the dc levels at these pins are disturbed, performance is compromised; therefore, signal coupling capacitors must be connected from the input signal to INHI and INLO. The input signal high-pass corner formed by the coupling capacitors and the internal resistances is fHIGH-PASS = 1/(2 x x 50 x C) (8) where C is in farads and fHIGH-PASS is in hertz. The input coupling capacitors must be large enough in value to pass the input signal frequency of interest. The other input pin should be RF accoupled to common (ground). Rev. 0 | Page 17 of 36 AD8363 TEMPERATURE SENSOR INTERFACE The AD8363 provides a temperature sensor output with an output voltage scaling factor of approximately 5 mV/C. The output is capable of sourcing 4 mA and sinking 50 A maximum at temperatures at or above 25C. If additional current sink capability is desired, an external resistor can be connected between the TEMP and COMM pins. The typical output voltage at 25C is approximately 1.4 V. VPOS INTERNAL VPAT TEMP 12k 4k 07368-041 The values in Table 4 were chosen to give the best drift performance at the high end of the usable dynamic range over the -40C to +85C temperature range. Compensating the device for the temperature drift using TCM1 and TCM2/PWDN allows for great flexibility and the user may wish to modify these values to optimize for another amplitude point in the dynamic range, for a different temperature range, or for an operating frequency other than those shown in Table 4. To find a new compensation point, VTCM1 and VTCM2 can be swept while monitoring VOUT over the temperature at the frequency and amplitude of interest. The optimal voltages for VTCM1 and VTCM2 to achieve minimum temperature drift at a given power and frequency are the values of VTCM1 and VTCM2 where VOUT has minimum movement. See the AD8364 and ADL5513 data sheets for more information. Varying VTCM1 and VTCM2 has only a very slight effect on VOUT at device temperatures near 25C; however, the compensation circuit has more and more effect, and is more and more necessary for best temperature drift performance, as the temperature departs farther from 25C. Figure 47 shows the effect on temperature drift performance at 25C and 85C as VTCM1 is varied but VTCM2 is held constant at 0.6 V. 3 COMM Figure 45. TEMP Interface Simplified Schematic VREF INTERFACE The VREF pin provides an internally generated voltage reference. The VREF voltage is a temperature stable 2.3 V reference that is capable of sourcing 4 mA and sinking 50 A maximum at temperatures at or above 25C. An external resistor can be connected between the VREF and COMM pins to provide additional current sink capability. The voltage on this pin can be used to drive the TCM1, TCM2/PWDN, and VTGT pins, if desired. VPOS INTERNAL VOLTAGE VREF 2 VTCM1 = 0.62V 1 ERROR (dB) 0 16k 07368-042 -1 VTCM1 = 0.42V 25C 85C COMM -2 Figure 46. VREF Interface Simplified Schematic -50 -40 -30 -20 RFIN (dBm) -10 0 10 07368-050 TEMPERATURE COMPENSATION INTERFACE While the AD8363 has a highly stable measurement output with respect to temperature, it uses proprietary techniques to make it even more stable. For optimal performance, the output temperature drift must be compensated for using the TCM1 and TCM2/ PWDN pins. The absolute value of compensation varies with frequency and VTGT. Table 4 shows the recommended voltages for the TCM1 and TCM2/PWDN pins to maintain the best temperature drift error over the rated temperature range (-40C < TA < 85C) when driven single-ended and using a VTGT = 1.4 V. Table 4. Recommended Voltages for TCM1 and TCM2/PWDN Frequency 100 MHz 900 MHz 1.9 GHz 2.14 GHz 2.6 GHz 3.8 GHz 5.8 GHz TCM1 (V) 0.47 0.5 0.52 0.52 0.54 0.56 0.88 TCM2/PWDN (V) 1.0 1.2 0.51 0.6 1.1 1.0 1.0 -3 -60 Figure 47. Error vs. Input Amplitude over Stepped VTCM1 Values, 25oC and 85oC, 2.14 GHz, VTCM2 = 0.6 V TCM1 primarily adjusts the intercept of the AD8363 at temperature. In this way, TCM1 can be thought of as a coarse adjustment to the compensation. Conversely, TCM2 performs a fine adjustment. For this reason, it is advised that when searching for compensation with VTCM1 and VTCM2, that VTCM1 be adjusted first, and when best performance is found, VTCM2 can then be adjusted for optimization. It is evident from Figure 47 that the temperature compensation circuit can be used to adjust for the lowest drift at any input amplitude of choice. Though not shown in Figure 47, a similar analysis can simultaneously be performed at -40C, or any other temperature within the operating range of the AD8363. Rev. 0 | Page 18 of 36 AD8363 Performance varies slightly from device to device; therefore, optimal VTCM1 and VTCM2 values must be arrived at statistically over a population of devices to be useful in mass production applications. The TCM1 and TCM2 pins have high input impedances, approximately 5 k and 500 k, respectively, and can be conveniently driven from an external source or from a fraction of VREF by using a resistor divider. VREF does change slightly with temperature and RF input amplitude (see Figure 41 and Figure 42); however, the amount of change is unlikely to result in a significant effect on the final temperature stability of the RF measurement system. Figure 48 shows a simplified schematic representation of TCM1. See the Power-Down Interface section for the TCM2 interface. VPOS ESD ESD 3k 3k ESD 07368-043 VSET INTERFACE The VSET interface has a high input impedance of 72 k. The voltage at VSET is converted to an internal current used to set the internal VGA gain. The VGA attenuation control is approximately 19 dB/V. GAIN ADJUST VSET 54k 18k 2.5k 07368-045 COMM Figure 50. VSET Interface Simplified Schematic OUTPUT INTERFACE TCM1 COMM Figure 48. TCM1 Interface Simplified Schematic POWER-DOWN INTERFACE The quiescent and disabled currents for the AD8363 at 25C are approximately 60 mA and 300 A, respectively. The dual function pin, TCM2/PWDN, is connected to a temperature compensation circuit as well as a power-down circuit. Typically, when PWDN is greater than VPOS - 0.1 V, the device is fully powered down. Figure 38 shows this characteristic as a function of VPWDN. Note that because of the design of this section of the AD8363, as VTCM2 passes through a narrow range at ~4.5 V (or ~VPOS - 0.5 V), the TCM2/PWDN pin sinks approximately 750 A. The source used to disable the AD8363 must have a sufficiently high current capability for this reason. Figure 35 shows the typical response times for various RF input levels. The output reaches within 0.1 dB of its steady-state value in approximately 35 s; however, the reference voltage is available to full accuracy in a much shorter time. This wake-up response varies depending on the input coupling and the capacitances, CHPF and CLPF. VPOS ESD SHUTDOWN POWER-UP CIRCUIT CIRCUIT TCM2/ PWDN 200 ESD 7k 200 7k VREF The output driver used in the AD8363 is different from the output stage on the AD8362. The AD8363 incorporates rail-torail output drivers with pull-up and pull-down capabilities. The closed-loop -3 dB bandwidth of the VOUT buffer with no load is approximately 58 MHz with a single-pole roll-off of -20 dB/dec. The output noise is approximately 45 nV/Hz at 100 kHz, which is independent of CLPF due to the architecture of the AD8363. VOUT can source and sink up to 10 mA. There is an internal load between VOUT and COMM of 2.5 k. VPOS ESD 2pF CLPF ESD 2k ESD VOUT COMM Figure 51. VOUT Interface Simplified Schematic 200 ESD COMM Figure 49. PWDN Interface Simplified Schematic Rev. 0 | Page 19 of 36 07368-044 INTERCEPT TEMPERATURE COMPENSATION 07368-046 500 AD8363 VTGT INTERFACE The target voltage can be set with an external source or by connecting the VREF pin (nominally 2.3 V) to the VTGT pin through a resistive voltage divider. With 1.4 V on the VTGT pin, the rms voltage that must be provided by the VGA to balance the AGC feedback loop is 1.4 V x 0.05 = 70 mV rms. Most of the characterization information in this data sheet was collected at VTGT = 1.4 V. Voltages higher and lower than this can be used; however, doing so increases or decreases the gain at the internal squaring cell, which results in a corresponding increase or decrease in intercept. This in turn affects the sensitivity and the usable measurement range. Because the gain of the squaring cell varies with temperature, oscillations or a loss in measurement range can result. For these reasons, do not reduce VTGT below 1.3 V. VPOS ESD g x X2 VTGT 50k ITGT BASIS FOR ERROR CALCULATIONS The slope and intercept used in the error plots are calculated using the coefficients of a linear regression performed on data collected in its central operating range. The error plots in the Typical Performance Characteristics section are shown in two formats: error from the ideal line and error with respect to 25C. The error from the ideal line is the decibel difference in VOUT from the ideal straight-line fit of VOUT calculated by the linearregression fit over the linear range of the detector, typically at 25C. The error in decibels is calculated by Error (dB) = (VOUT - Slope x (PIN - PZ))/Slope (12) where PZ is the x-axis intercept expressed in dBm (the input amplitude that produces a 0 V output, if such an output is possible). The linear range of the detector was assumed to be -20 dBm to -40 dBm. The error from the ideal line is not a measure of absolute accuracy because it is calculated using the slope and intercept of each device. However, it verifies the linearity and the effect of temperature and modulation on the response of the device. Examples of this type of plot are Figure 3 and Figure 4. The slope and intercept that form the ideal line are those at 25C with CW modulation. Figure 27, Figure 28, Figure 30, and Figure 31 show the error with various popular forms of modulation with respect to the ideal CW line. This method for calculating error is accurate assuming each device is calibrated at room temperature and/or CW modulation, as appropriate. In the second plot format, the VOUT voltage at a given input amplitude and temperature is subtracted from the corresponding VOUT at 25C and then divided by the 25C slope to obtain an error in decibels. This type of plot does not provide any information on the linear-in-dB performance of the device; it merely shows the decibel equivalent of the deviation of VOUT over temperature, given a calibration at 25C. When calculating error from any one particular calibration point, this error format is accurate. It is accurate over the full range shown on the plot assuming enough calibration points are used. Figure 5 shows this plot type. The error calculation for Figure 32 is in the same method as the first type previously mentioned, except that instead of varying the operating temperature of the device, the operating voltage was varied and the error is expressed with the nominal (5 V) response as the base response. The error calculations for Figure 26 are similar to that for the VOUT plots. The slope and intercept of the VTEMP function vs. temperature were determined and applied as follows: Error (C) = (VTEMP - Slope x (Temp - TZ))/Slope (13) where: TZ is the x-axis intercept expressed in degrees Celsius (the temperature that would result in a VTEMP of 0 V (an extrapolation because this is not possible). Temp is the temperature of the AD8363 in degrees Celsius. Slope is expressed in V/C. VTEMP is the voltage at the TEMP pin at that temperature. ESD 50k ESD 10k COMM Figure 52. VTGT Interface Simplified Schematic OPERATION TO 125C Most of the information in this data sheet describes operation up to, but not exceeding, 85C. Operation up to 125C is possible; however, the performance of the AD8363 above 85C can be degraded. Figure 53 shows the typical operation at 125C as compared to other temperatures using the TCM1 and TCM2 values in Table 4. Temperature compensation can be optimized for operation above 85C by modifying the voltages on the TCM1 and TCM2 pins from those shown in Table 4. 6 -40C +25C +85C +125C 3 5 OUTPUT VOLTAGE (V) 2 4 1 ERROR (dB) 07368-053 3 0 2 INHI INPUT VTCM1 = 0.52V, VTCM2 = 0.6V -1 1 -2 0 -60 -50 -40 -30 -20 PIN (dBm) -10 0 -3 10 Figure 53. VOUT and Log Conformance Error vs. Input Amplitude at 2.14 GHz, -40C to +125C 07368-047 Rev. 0 | Page 20 of 36 AD8363 MEASUREMENT MODE BASIC CONNECTIONS The AD8363 requires a single supply of nominally 5 V. The supply is connected to the two supply pins, VPOS. Decouple the pins using two capacitors with values equal or similar to those shown in Figure 54. These capacitors must provide a low impedance over the full frequency range of the input, and they should be placed as close as possible to the VPOS pins. Use two different capacitor values in parallel to provide a broadband ac short to ground. Input signals can be applied differentially or single-ended; however, in both cases, the input impedance is 50 . Most performance information in this data sheet was derived with a single-ended drive. The optimal measurement range is achieved using a singleended drive on the INHI pin at frequencies below 2.6 GHz (as shown in Figure 54), and likewise, optimal performance is achieved using the INLO pin above 2.6 GHz (similar to Figure 54; except INLO is ac-coupled to the input and INHI is ac-coupled to ground). VPOS2 VREF C7 0.1F C5 100pF The AD8363 is placed in measurement mode by connecting VOUT to VSET. This closes the AGC loop within the device with VOUT representing the VGA control voltage, which is required to present the correct rms voltage at the input of the internal square law detector. As the input signal is swept over its nominal input dynamic range of -50 dBm to 0 dBm, the output swings from approximately 0 V to a high value of approximately 3 V. R11 1.4k R10 845 12 VTGT 11 VREF 10 VPOS 9 COMM TEMP C10 0.1F LOW FREQUENCY INPUT 13 14 15 NC INHI INLO TCM2/PWDN TEMP 8 7 6 5 C9 0.1F VOUT AD8363 DUT1 VSET VOUT CLPF COMM C12 0.1F TCM1 16 TCM1 1 2 3 VPOS CHPF 4 PADDLE AGND C3 OPEN C4 100pF C13 0.1F TCM2/PWDN VPOS1 Figure 54. Measurement Mode Basic Connections Rev. 0 | Page 21 of 36 07368-062 AD8363 DEVICE CALIBRATION AND ERROR CALCULATION The measured transfer function of the AD8363 at 2.14 GHz is shown in Figure 55. It shows plots of both output voltage vs. input amplitude (power) and calculated error vs. input amplitude (power). As the input power varies from -50 dBm to 0 dBm, the output voltage varies from 0.25 V to about 2.8 V. 5.0 4.5 +25C -40C +85C 2.5 The log conformance error is the deviation of the detector from the ideal calculated power and is given by Error (dB) = (VOUT(MEASURED) - VOUT(IDEAL))/Slope (18) Figure 56 includes a plot of the error at 25C, the temperature at which the log amp is calibrated. Note that the error is not zero because the detector does not perfectly follow the ideal straight line. The error at the calibration points (in this case, -40 dBm and -21 dBm) are, however, equal to zero by definition. Note that Figure 55 is slightly different from those found in the Typical Performance Characteristics section; its slope and intercept are calculated using a two-point calculation and not based on multiple points, as was used for the Typical Performance Characteristics. Figure 55 also includes error plots for the output voltage at -40C and +85C. These error plots are calculated using the slope and intercept at 25C. Another way of saying this is that the hot and cold temperatures are calculated with respect to the output voltage at ambient, and by definition, the error at ambient becomes equal to 0. This is consistent with calibration in a mass production environment, where calibration at temperature is not practical. 5.0 4.5 +25C -40C +85C 2.5 OUTPUT VOLTAGE, VOUT (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.5 0.5 -0.5 -1.5 -50 -40 -30 -20 PIN, INHI (dBm) -10 0 Figure 55. 2.14 GHz Transfer Function Using Two-Point Calibration OUTPUT VOLTAGE, VOUT (V) Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. The equation for output voltage can be written as VOUT = Slope x (PIN - Intercept) (14) where: Slope is the change in output voltage divided by the change in power (dB). Intercept is the calculated input power level at which the output voltage would be 0 V. (Note that Intercept is a theoretical value; the output voltage can never achieve 0 V). In general, calibration is performed by applying two (or more) known signal levels into the input of the AD8363 and by measuring the corresponding output voltages. The calibration points are generally within the linear-in-dB operating range of the device (see the Specifications section for more details). The slope and intercept are calculated as follows: Slope = (VOUT1 - VOUT2)/(PIN1 - PIN2) Intercept = PIN1 - (VOUT1/Slope) (15) (16) 07368-064 0 -60 -2.5 10 ERROR (dB) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.5 0.5 -0.5 -1.5 -50 -40 -30 -20 PIN, INHI (dBm) -10 0 Figure 56. 2.14 GHz Transfer Function Using a Three-Point Calibration SELECTING AND INCREASING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE Choose the amount and location of the calibration points carefully because they can optimize the performance of the detector. In some applications, increasing the dynamic range of the AD8363 may be desirable; however, in others, very high accuracy is required at one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. These objectives can be achieved by the proper selection of the amount and location of the calibration points. The previous formula for intercept is a shorthand formula based upon Equation 14 and the assumption that the AD8363 is operating within the linear-in-dB operating range. When the slope and intercept are calculated, an equation can be written that allows the calculation of the ideal input power based on the output voltage of the detector. PIN (unknown) = (VOUT1(MEASURED)/Slope) + Intercept (17) Rev. 0 | Page 22 of 36 07368-065 0 -60 -2.5 10 ERROR (dB) AD8363 Increasing the amount of calibration points can increase the accuracy of the room temperature performance over a select power level. Figure 56 shows the same measured data as Figure 55; except that one calibration point was added at -7 dBm giving an increase in room temperature linearity between -20 dBm to +4 dBm. Figure 56 is similar to Figure 14, except Figure 14 includes more parts and assumes many more calibration points, specifically 1 dB steps from -20 dBm to -40 dBm. Even though a large amount of calibration points is less practical, Figure 14 is helpful because it shows the true temperature performance no matter the location of the calibration point. As can be seen from both Figure 14 and Figure 56, the temperature performance tends to change at power levels above -15 dBm. As shown in Figure 14, because the distribution of temperature performance is tight for the higher power levels, VTCM1 and VTCM2 can be optimized for the higher power levels, or a separate offset can be placed in the calibration routine that adds offsets for changes in temperature. Figure 57 shows a two-point calibration like Figure 55 but the calibration points were changed from -40 dBm and -21 dBm to -39 dBm and -11 dBm. This demonstrates how calibration points can be adjusted to increase dynamic range at the expense of linearity. The higher power calibration point was moved to a point where the AD8363 is not as linear. At 25C, there is an error of 0 dB at the calibration points. Note that the range over which the AD8363 maintains an error of <0.5 dB is extended to +53 dB at 25C. The disadvantage of this approach is that linearity suffers and the linearity at -25 dBm degrades by about 0.2 dB and the error at +3 dBm increases by about 0.7 dB. 5.0 4.5 +25C -40C +85C 2.5 ALTERING THE SLOPE None of the changes to operating conditions discussed so far effect the AD8363 logarithmic slope. The slope of the AD8363 can be easily increased or decreased. To reduce the slope, add a voltage divider on the output, VOUT. To increase the slope, control the fraction of VOUT that is fed back to the setpoint interface at the VSET pin. When the full signal from VOUT is applied to VSET, the slope assumes its nominal value of 52 mV/dB. It can be increased by including a voltage divider between these pins, as shown in Figure 58. 8 TEMP 7 VSET R1 6 VOUT R2 5 CLPF Figure 58. Altering the Slope Use moderately low resistance values to minimize the scaling errors from the approximately 72 k input resistance at the VSET pin. Note that this resistor string also loads the output, and eventually, it reduces the load driving capabilities, if very low values are used. Equation 19 can be used to calculate the resistor values. R1 = R2' (SD/52 - 1) where: SD is the desired slope, expressed in mV/dB. R2' is the value of R2 in parallel with 72 k. The typical slope of the AD8363 is 52; adjust this as needed. Figure 59 shows a comparison between the regular slope of a part and when the slope is doubled. For this example, R1 = 1.65 k and R2 = 1.69 k (R2' = 1.65 k). The initial slope was 52 mV/dB, and it increased to 104 mV/dB. The choice of 100 mV/dB scaling is useful when the output is applied to a digital voltmeter because the displayed number directly reads as a decibel quantity with only a decimal point shift. When measuring a particular section of the input range, operating at a high slope is useful. With a slope of 104 mV/dB, a measurement range of 50 dB corresponds to a 5.2 V change in VOUT, exceeding the capacity of the output stage of the AD8363, when operating on a 5 V supply. Figure 59 clearly shows this effect. (19) OUTPUT VOLTAGE, VOUT (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.5 0.5 -0.5 -1.5 -50 -40 -30 -20 PIN, INHI (dBm) -10 0 Figure 57. 2.14 GHz Transfer Function with Change in Two-Point Calibration Points Rev. 0 | Page 23 of 36 07368-066 0 -60 -2.5 10 ERROR (dB) 07368-067 AD8363 When interfacing with an ADC, use as much of the input dynamic range as possible to maximize the resolution. It is also important that the VOUT voltage of the AD8363 does not exceed the range accepted by the input of the ADC for the power levels of interest. This must take into account the part-to-part variation of the AD8363 and its variation over temperature. This is especially important when the slope is increased. The VOUT distribution is well characterized at major frequencies bands in the Typical Performance Characteristics section. Most of the VOUT variation from part to part and over temperature is due to an intercept shift; therefore, increasing the slope should not increase the distribution greatly. When increasing the slope, the intercept does not change greatly. In Figure 59, the intercept changed by 0.2 dB after the slope change. Therefore, it is possible to calculate the maximum voltage for a particular power level by using the following equation: NewVMAX = OldVMAX (New Slope/Old Slope) (20) For example, Figure 10 shows that the maximum voltage for a -20 dBm input at 1.9 GHz is 2 V. If the slope is doubled from 52 mV/dB to 104 mV/dB, the maximum voltage at the new slope is 4 V. The REFIN voltage of the ADC (the voltage that sets the maximum readable voltage in the ADC) is set to 4.16 V, assuming a 3 dB margin on its input. 5.0 4.5 4.0 3.5 100mV SLOPE 50mV SLOPE ERROR 50mV SLOPE ERROR 100mV SLOPE 5 4 3 2 1 0 -1 -2 -3 -4 0 5 07368-068 The input offset voltage varies depending on the actual gain at which the VGA is operating and, therefore, on the input signal amplitude. When a large CHPF value is used, the offset correction process can lag the more rapid changes in the gain of the VGA, which can increase the time required for the loop to fully settle for a given steady input amplitude. This can manifest itself in a jumpy, seemingly oscillatory response of the AD8363. In measurement mode, take care in choosing CHPF and CLPF because there is a potential to create oscillations. In general, make the capacitance on the CLPF pin as large as possible; there is no maximum on the amount of capacitance that can be added to this pin. Generally, there is no need for an external capacitor on the CHPF pin; therefore, the pin can be left open. However, when trying to get a fast response time and/or when working at low frequencies, extra care in choosing the proper capacitance values for CHPF and CLPF is prudent. With the gain control pin (VSET) connected to VOUT, VSET can slew at a rate determined by the on-chip squaring cell and CLPF. When VSET is changing with time, the dc offsets in the VGA also vary with time. The speed at which VSET slews can create a time varying offset that falls within the high-pass corner set by CHPF. Therefore, in measurement mode, take care to set CLPF appropriately to reduce the slew. It is also worth noting that most of the typical performance data was derived with CLPF = 3.9 nF and CHPF = 2.7 nF and with a CW waveform. The minimum appropriate CLPF based on slew rate limitations is as follows CLPF > 20 x 10-3/FREQRFIN (21) where: CLPF is in farads. FREQRFIN is in hertz. This takes into account the on-chip 25 pF capacitor, CF, in parallel with CLPF. However, because there are other internal device time delays that affect loop stability, use a minimum CLPF of 390 pF. The minimum appropriate CHPF for a given high-pass pole frequency is CHPF = 29.2 x 10-6/FHPPOLE - 25 pF where FHPPOLE is in hertz. The subtraction of 25 pF is a result of the on-chip 25 pF capacitor in parallel with the external CHPF. Typically, choose CHPF to give a pole (3 dB corner) at least 1 decade below the desired signal frequency. Note that the high pass corner of the offset compensation system is approximately 1 MHz without an external CHPF; therefore, adding an external capacitor lowers the corner frequency. (22) VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 PIN (dBm) -5 10 Figure 59. Slope Change from 52 mV/dB to 104 mV/dB, Frequency = 2.14 GHz OFFSET COMPENSATION/MINIMUM CLPF AND MAXIMUM CHPF CAPACITANCE VALUES An offset-nulling loop is used to address small dc offsets within the internal VGA as shown in Figure 60. The high-pass corner frequency of this loop is set to about 1 MHz using an on-chip 25 pF capacitor, which is sufficiently low for most RF applications. The high-pass corner can be lowered further by connecting a capacitor between CHPF and VPOS. ERROR (dB) Rev. 0 | Page 24 of 36 AD8363 The following example illustrates the proper selection of the input coupling capacitors, minimum CLPF, and maximum CHPF when using the AD8363 in measurement mode for a 1 GHz input signal. 1. Choose the input coupling capacitors that have a 3 dB corner at least one decade below the input signal frequency. From Equation 8, C > 10/(2 x x RFIN x 50) = 32 pF minimum. According to this calculation, 32 pF is sufficient; however, the input coupling capacitors should be a much larger value, typically 0.1 F. The offset compensation circuit, which is connected to CHPF, should be the true determinant of the system high-pass corner frequency and not the input coupling capactitors. With 0.1 F coupling capacitors, signals as low as 32 kHz can couple to the input, which will be well below the system high-pass frequency. Choose CLPF to reduce instabilities due to VSET slew rate. See Equation 21, where FRQRFIN = 1 GHz, and this results in CLPF > 20 pF. However, as previously mentioned, values below 390 pF are not recommended. For this reason, a 470 pF capacitor was chosen. In addition, if fast response times are not required, an even larger CLPF value than given here should be chosen. Choose CHPF to set a 3 dB corner to the offset compensation system. See Equation 22, where FHPPOLE is in this case 100 MHz, one decade below the desired signal. This results in a negative number and, obviously, a negative value is not practical. Because the high-pass corner frequency is already 1 MHz, this result simply illustrates that the appropriate solution is to use no external CHPF capacitor. CHOOSING A VALUE FOR CLPF The Small Signal Loop Response section and the Offset Compensation/Minimum CLPF and Maximum CHPF Capacitance Values section discussed how to choose the minimum value capacitance for CLPF based on a minimum capacitance of 390 pF, slew rate limitation, and frequency of operation. Using the minimum value for CLPF allows the quickest response time for pulsed type waveforms (such as WiMAX) but also allows the most residual ripple on the output caused by the pseudorandom modulation waveform. There is not a maximum for the capacitance that can be applied to the CLPF pin, and in most situations, a large enough capacitor can be added to remove the residual ripple caused by the modulation and yet allow a fast enough response to changes in input power. Figure 61 shows how residual ripple, rise time, and fall time vary with filter capacitance when the AD8363 is driven by a single carrier CDMA2000 9CH SR1 signal at 2.14 GHz. The rise time and fall time is based on a signal that is pulsed between no signal and 10 dBm but is faster if the input power change is less. 400 350 2800 2450 RESIDUAL RIPPLE (mV) RISE TIME (s) FALL TIME (s) 2100 1750 1400 1050 700 350 07368-069 2. 3. RESIDUAL RIPPLE (mV p-p) RISE TIME (s) 300 250 200 150 100 50 0 0 10 It can also be noted that per Equation 9 FreqLP 1.83 x ITGT/(CLPF) A CLPF of 470 pF results in a small signal low-pass corner frequency of approximately 144 kHz. This reflects the bandwidth of the measurement system, and how fast the user can expect changes on the output. It does not imply any limitations on the input RF carrier frequency. VPOS 25pF (INTERNAL) 110 VGA gm1 RFIN gm gm2 110 CHPF 1pF 1pF 20 30 40 50 60 70 CLPF CAPACITANCE (nF) 80 90 0 100 Figure 61. Residual Ripple, Rise Time, and Fall Time vs. CLPF Capacitance, Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz with 10 dBm Pulse A=1 VX 40dB g x X2 IRF Figure 60. Offset Compensation Circuit Rev. 0 | Page 25 of 36 07368-040 FALL TIME (s) AD8363 Table 5 shows the recommended values of CLPF for popular modulation schemes. For nonpulsed waveforms, increase CLPF until the residual output noise falls below 50 mV (0.5 dB). In each case, the capacitor can be increased to further reduce the noise. A 10% to 90% step response to an input step is also listed. Where the increased response time is unacceptably high, reduce CLPF, which increases the noise on the output. Due to the random nature of the output ripple, if it is sampled by an ADC, averaging in the digital domain further reduces the residual noise. Table 5 gives CLPF values to minimize noise while trying to keep a reasonable response time. For nonpulsed type waveforms, averaging is not required on the output. For pulsed waveforms, the smaller the noise, the less averaging is needed on the output. System specifications determine the necessary rise time and fall time. For example, the suggested CLPF value for WiMAX assumes that it is not necessary to measure the power in the preamble. Figure 62 shows how the rise time cuts off the preamble. Note that the power in the preamble can be easily measured; however, the CLPF value would have to be reduced slightly, and the noise in the main signal would increase. T CH1 RISE 81.78s CH1 FALL 1.337ms 1 CH1 500mV M 1.00ms T 10.00% A CH1 600mV Figure 62. AD8363 Output to a WiMAX 802.16, 64 QAM, 256 Subcarriers, 10 MHz Bandwidth Signal with CLPF = 0.027 F As shown in Figure 61, the fall time for the AD8363 increases faster than the rise time with an increase in CLPF capacitance. Some pulse-type modulation standards require a fast fall time as well as a fast rise time, and in all cases, less output ripple is desired. Placing an RC filter on the output reduces the ripple, according to the frequency content of the ripple and the filter's poles and zeros. Using an RC output filter also changes the rise and fall time vs. the output ripple response as compared to increasing the CLPF capacitance. Table 5. Recommended CLPF Values for Various Modulation Schemes Modulation/Standard W-CDMA, 1Carrier, TM1-64 W-CDMA, 1Carrier, TM1-64 (EVDO) W-CDMA 4Carrier, TM1-64 CDMA2000, 1Carrier, 9CH CDMA2000, 3Carrier, 9CH WiMAX 802.16 , 64 QAM, 256 Subcarriers, 10 MHz Bandwidth 6C TD-SCDMA 1C TD-SCDMA Crest Factor (dB) 12 12 11 9.1 11 14 14 11.4 CLPF 0.1 F 3900 pF 0.1 F 0.1 F 0.1 F 0.027 F 0.01 F 0.01 F Residual Ripple (mV p-p) 15 150 8 10 13 10 69 75 Response Time (Rise/Fall) 10% to 90% 236 s/2.9 ms 8.5 s/100 s 240 s/2.99 ms 210 s/3.1 ms 215 s/3.14 ms 83 s/1.35 ms 24 s/207 s 24 s /198 s Rev. 0 | Page 26 of 36 07368-054 AD8363 Figure 63 shows the response for a 2.14 GHz pulsed signal, with CLPF = 3900 pF. The residual ripple from a single carrier CDMA2000 9CH SR1 signal is 150 mV p-p. (The ripple is not shown in Figure 63. The ripple was measured separately.) Figure 64 shows the response for a 2.14 GHz pulse signal with a CLPF of 390 pF and an output filter that consists of a series 75 resistor (closest to the output) followed by a 0.15 F capacitor to ground. The residual ripple for this configuration is also 150 mV p-p. Note that the rise time is faster and the fall time is slower when the larger CLPF is used to obtain a 150 mV p-p ripple. T CONTROLLER MODE BASIC CONNECTIONS In addition to being a measurement device, the AD8363 can also be configured to control rms signal levels, as shown in Figure 65. The RF input to the device is configured as it was in measurement mode and either input can be used. A directional coupler taps off some of the power being generated by the VGA. If loss in the main signal path is not a concern, and there are no issues with reflected energy from the next stage in the signal chain, a power splitter can be used instead of a directional coupler. Some additional attenuation may be required to set the maximum input signal at the AD8363 to be equal to the recommended maximum input level for optimum linearity and temperature stability at the frequency of operation. The VSET and VOUT pins are no longer shorted together. VOUT now provides a bias or gain control voltage to the VGA. The gain control sense of the VGA must be negative and monotonic, that is, increasing voltage tends to decrease gain. However, the gain control transfer function of the device does not need to be well controlled or particularly linear. If the gain control sense of the VGA is positive, an inverting op amp circuit with a dc offset shift can be used between the AD8363 and the VGA to keep the gain control voltage in the 0.03 V to 4.8 V range. VSET becomes the set-point input to the system. This can be driven by a DAC, as shown in Figure 65, if the output power is expected to vary, or it can simply be driven by a stable reference voltage, if constant output power is required. This DAC should have an output swing that covers the 0.15 V to 3.5 V range. The AD7391 and AD7393 serial input and parallel input 10-bit DACs provide adequate resolution (4 mV/bit) and an adjustable output swing over 4.5 V. VGA OR VVA (OUTPUT POWER DECREASES AS VAPC INCREASES) VAPC ATTENUATOR (0.03V TO 4.8V AVAILABLE SWING) VOUT C10 INHI CH1 RISE 8.480s CH1 FALL 101.4s CH1 AMPL 2.37V 1 CH1 500mV M 100s T 10.40% A CH1 720mV Figure 63. Pulse Response with CLPF = 3900 pF Resulting in a 150 mV p-p Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz T 8 7 6 5 TEMP VSET VOUT CLPF 390pF 75 OSCILLOSCOPE PROBE 0.15F CH1 RISE 13.66s CH1 FALL 35.32s CH1 AMPL 2.36V 1 07368-070 PIN POUT CH1 500mV M 100s T 10.60% A CH1 750mV Figure 64. Pulse Response with CLPF = 390 pF and Series 75 Resistor Followed by a 0.15 F Capacitor to Ground, Resulting in a 150 mV p-p Ripple for a Single Carrier CDMA2000 9CH SR1 Signal at 2.14 GHz RF PULSE RESPONSE The response of the AD8363 to pulsed RF waveforms is affected by VTGT. Referring to Figure 33 and Figure 34, there is a period of inactivity between the start of the RF waveform and the time at which VOUT begins to show a reaction. This happens as a result of the implementation of the balancing of the squarer currents within the AD8363. This delay can be reduced by decreasing VTGT; however, as previously noted in the VTGT Interface section, this has implications on the sensitivity, intercept, and dynamic range. While the delay is reduced, reducing VTGT increases the rise and fall time of VOUT. 07368-071 AD8363 INLO C12 VSET CLPF C9 SEE TEXT (0.15V TO 3.5V) DAC Figure 65. Controller Mode Operation for Automatic Power Control Rev. 0 | Page 27 of 36 07368-063 AD8363 When VSET is set to a particular value, the AD8363 compares this value to the equivalent input power present at the RF input. If these two values do not match, VOUT increases or decreases in an effort to balance the system. The dominant pole of the error amplifier/integrator circuit that drives VOUT is set by the capacitance on the CLPF pin; some experimentation may be necessary to choose the right value for this capacitor. In general, CLPF should be chosen to provide stable loop operation for the complete output power control range. If the slope (in dB/V) of the gain control transfer function of the VGA is not constant, CLPF must be chosen to guarantee a stable loop when the gain control slope is at its maximum. In addition, CLPF must provide adequate averaging to the internal low range squaring detector so that the rms computation is valid. Larger values of CLPF tend to make the loop less responsive. The relationship between VSET and the RF input follows the measurement mode behavior of the device. For example, Figure 6 shows the measurement mode transfer function at 900 MHz and that an input power of -10 dBm yields an output voltage of approximately 2.5 V. Therefore, in controller mode, if VSET is 2.5 V, the AD8363 output would go to whatever voltage is necessary to set the AD8363 input power to -10 dBm. The low end power is limited by the maximum gain of the VGA (ADL5330) and can be increased by using a VGA with more gain. The temperature performance is directly related to the temperature performance of the AD8363 at 2.14 GHz and -26 dBm, using TCM1 = 0.52 V and TCM2 = 0.6 V. All other temperature variations are removed by the AD8363. For more information on controller mode, see the Controller Mode Basic Connections section. PIN C5 100pF ADL5330 INHI INLO OPHI OPLO GAIN T1 C11 100pF 10dB COUPLER T2 POUT C6 100pF C12 100pF AD8062 10k 10k 10k 10k 5V C10 0.1F INHI CONSTANT OUTPUT POWER OPERATION In controller mode, the AD8363 can be used to hold the output power of a VGA stable over a broad temperature/input power range. This is useful in topologies where a transmit card is driving an HPA, or when connecting any two power sensitive modules together. Figure 66 shows a schematic of a circuit setup that holds the output power to approximately -26 dBm at 2.14 GHz, when the input power is varied over a 40 dB dynamic range. Figure 67 shows the results. A portion of the output power is coupled off using a 10 dB coupler, and it is then fed into the AD8363. VSET is fixed at 0.95 V, which forces to AD8363 output voltage to control the ADL5330 so that the input to the AD8363 is approximately -36 dBm. If the AD8363 was in measurement mode and a -36 dBm input power is applied, the output voltage would be 0.95 V. A general-purpose, rail-to-rail op amp (AD8062) is used to invert the slope of the AD8363 so that the gain of the ADL5330 decreases as the AD8363 control voltage increases. The output power is controlled to a 10 dB higher power level than that seen by the AD8363 due to the coupler. The high end power is limited by the linearity of the VGA (ADL5330) with high attenuation and can be increased by using a higher linearity VGA. 0.52V TCM1 0.6V TCM2 VOUT AD8363 INLO CLPF C9 0.1F 0.95V C12 0.1F 07368-072 VSET Figure 66. Constant Power Circuit -25.0 -25.5 -26.0 POUT (dBm) -26.5 -27.0 -20C -40C +85C +25C 0C -35 -30 -25 -20 -15 PIN (dBm) -10 -5 0 07368-055 -27.5 -28.0 -40 Figure 67. Performance of the Circuit Shown in Figure 66 Rev. 0 | Page 28 of 36 AD8363 DESCRIPTION OF RF CHARACTERIZATION The general hardware configuration used for most of the AD8363 characterization is shown in Figure 68. The AD8363 was driven in a single-ended configuration for all characterization. Characterization of the AD8363 employed a multisite test strategy. Several AD8363 devices mounted on circuit boards constructed with Rogers 3006 material was simultaneously inserted into a remotely-controlled thermal test chamber. A Keithley S46 RF switching network connected an Agilent E8251A signal source to the appropriate device under test. An Agilent 34980A switch matrix provided switching of dc power and metering for the test sites. A PC running Agilent VEE Pro controlled the signal source, switching, and chamber temperature. A voltmeter measured the subsequent response to the stimulus, and the results were stored in a database for later analysis. In this way, multiple AD8363 devices were characterized over amplitude, frequency, and temperature in a minimum amount of time. The RF stimulus amplitude was calibrated up to the connector of the circuit board that carries the AD8363. However, the calibration does not account for the slight losses due to the connector and the traces from the connector to the device under test. For this reason, there is a small absolute amplitude error (<0.5 dB) not accounted for in the characterization data. This implies a slight error in the reported intercept; however, this is generally not important because the slope and the relative accuracy of the AD8363 are not affected. The typical performance data was derived with CLPF = 3.9 nF and CHPF = 2.7 nF with a CW waveform. AGILENT E3631A DC POWER SUPPLIES AGILENT 34980A SWITCH MATRIX/ DC METER AD8363 CHARACTERIZATION BOARD - TEST SITE 1 AGILENT E8251A MICROWAVE SIGNAL GENERATOR KEITHLEY S46 MICROWAVE SWITCH AD8363 CHARACTERIZATION BOARD - TEST SITE 2 AD8363 PERSONAL COMPUTER CHARACTERIZATION BOARD - TEST SITE 3 07368-075 RF DC DATA AND CONTROL Figure 68. General RF Characterization Configuration Rev. 0 | Page 29 of 36 AD8363 EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS Figure 69 to Figure 73 show the evaluation board for the AD8363. VTGT VREF VPOS C7 0.1F R7 0 R11 1.4k R10 845 VPOS R8 0 R14 0 C5 100pF 12 11 10 9 VTGT VPOS COMM VREF TEMP R2 OPEN TEMP 8 7 6 5 C9 0.1F R5 0 PADDLE AGND R6 0 VSET C10 0.1F IN C11 OPEN 13 14 15 R13 OPEN VOUT NC INHI INLO TCM1 AD8363 DUT1 TCM2/PWDN VSET VOUT CLPF R1 0 R15 0 VOUT C6 OPEN C12 0.1F TCM1 R17 OPEN 16 R18 OPEN COMM VPOS CHPF C8 OPEN VREFC TCM2/PWDN 1 2 3 4 C3 OPEN R16 0 VPOSC VREFC VPOS1 C4 100pF C13 0.1F GND GNDI R12 OPEN R9 OPEN Figure 69. Evaluation Board Schematic Table 6. Bill of Materials Component C6, C10, C11, C12 Function/Notes Input. The AD8363 is single ended driven. At frequencies 2.6 GHz, the best dynamic range is achieved by driving Pin 14 (INHI). When driving INHI, populate C10 and C12 with an appropriate capacitor value for the frequency of operation and leave C6 and C11 open. For frequencies >2.6 GHz, additional dynamic range can be achieved by driving Pin 15 (INLO). When driving INLO, populate C6 and C11 with an appropriate capacitor value for the frequency of operation and leave C10 and C12 open. VTGT. R10 and R11 are set up to provide 1.4 V to VTGT from VREF. If R10 and R11 are removed, an external voltage can be used. Alternatively, R7 and R11 can be used to form a voltage divider for an external reference. Default Value C6 = open, C10 = 0.1 F, C11 = open C12 = 0.1 F R7 = 0 , R8 = 0 , R10 = 845 , R11 = 1.4 k C4 = 100 pF, C5 = 100 pF, C7 = 0.1F, C13 = 0.1F, R14 = 0 , R16 = 0 R7, R8, R10, R11 C4, C5, C7, C13, R14, R16 Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the AD8363, a 0 series resistor, and a 0.1 F capacitor placed close to the power supply input pin. The 0 resistor can be replaced with a larger resistor to add more filtering; however, it is at the expense of a voltage drop. Rev. 0 | Page 30 of 36 07368-074 AD8363 Component R1, R2, R6, R13, R15 Function/Notes Output Interface (Default Configuration) in Measurement Mode. In this mode, a portion of the output voltage is fed back to the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope at VOUT is increased by reducing the portion of VOUT that is fed back to VSET. If a fast responding output is expected, the 0 resistor (R15) can be removed to reduce parasitics on the output. Output Interface in Controller Mode. In this mode, R6 must be open and R13 must have a 0 resistor. In controller mode, the AD8363 can control the gain of an external component. A setpoint voltage is applied to the VSET pin, the value of which corresponds to the desired RF input signal level applied to the AD8363. If a fast responding output is expected, the 0 resistor (R15) can be removed to reduce parasitics on the output. Low-Pass Filter Capacitors, CLPF. The low-pass filter capacitors reduce the noise on the output and affect the pulse response time of the AD8363. This capacitor should be as large as possible. The smallest CLPF capacitance should be 390 pF. R5, when set to a value other than 0 , is used in conjunction with C8 and C9 to modify the loop transfer function and change the loop dynamics in controller mode. CHPF Capacitor. The CHPF capacitor introduces a high-pass filter affect into the AD8363 transfer function and can also affect the response time. The CHPF capacitor should be as small as possible and connect to VPOS when used. No capacitor is needed for input frequencies greater than 10 MHz. TCM2/PWDN. The TCM2/PWDN pin controls the amount of nonlinear intercept temperature compensation and/or shuts down the device. The evaluation board is configured to control this from a test loop, but VREF can also be used by the voltage divider created by R9 and R12. TCM1. TCM1 controls the temperature compensation (5 k impedance). The evaluation board is configured to control this from a test loop, but VREF can also be used by the voltage divider created by R17 and R18. Due to the relatively low impedance of the TCM1 pin and the limited current of the VREF pin, care should be taken when choosing the R17 and R18 values. Connect the paddle to both a thermal and electrical ground. Default Value R1 = 0 , R2 = open, R6 = 0 , R13 = open, R15 = 0 C8, C9, R5 C8 = open, C9 = 0.1 F, R5 = 0 C3 = open C3 R9, R12 R9 = open, R12 = open R17 = open, R18 = open R17, R18 Paddle Rev. 0 | Page 31 of 36 AD8363 ASSEMBLY DRAWINGS 07368-058 Figure 70. Evaluation Board Layout, Top Side Figure 72. Evaluation Board Assembly, Top Side 07368-059 Figure 71. Evaluation Board Layout, Bottom Side Figure 73. Evaluation Board Assembly, Bottom Side Rev. 0 | Page 32 of 36 07368-061 07368-060 AD8363 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 13 16 0.60 MAX PIN 1 INDICATOR 1 PIN 1 INDICATOR TOP VIEW 0.65 BSC 3.75 BSC SQ 0.50 0.40 0.30 12 EXPOSED PAD (BOTTOM VIEW) 2.50 2.35 SQ 2.20 4 9 8 5 0.25 MIN 1.95 BSC 12 MAX 1.00 0.85 0.80 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 74. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4mm Body, Very Thin Quad (CP-16-10) Dimensions shown in millimeters ORDERING GUIDE Model AD8363ACPZ-R7 1 AD8363ACPZ-WP1 AD8363-EVALZ1 1 Temperature Range -40C to +125C -40C to +125C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-16-10 CP-16-10 082008-A SEATING PLANE 0.35 0.30 0.25 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Ordering Quantity 1,500 64 Z = RoHS Compliant Part. Rev. 0 | Page 33 of 36 AD8363 NOTES Rev. 0 | Page 34 of 36 AD8363 NOTES Rev. 0 | Page 35 of 36 AD8363 NOTES (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07368-0-5/09(0) Rev. 0 | Page 36 of 36 |
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